The present invention generally relates to a semiconductor memory and, more particularly, to an electrically erasable and programmable read only memory (EEPROM) having an insulating film through which a charge is transferred so that the content of a memory cell is electrically rewritten.
Recently, two different types of EEPROM have been proposed, one of which has a configuration which utilizes a trap formed at an interface between insulating films of different types, and the other type has a configuration which utilizes a floating gate. The two types of EEPROM utilize the tunnel effect in data write and erase. Thus, current generated at the time of data write or erase is extremely small. As a result of small current, a variety of EEPROMs have been developed. For example, an EEPROM has a mode in which data relating to all bits can be erased at the same time, or alternatively has a mode in which data can be written or erased per page unit. Generally, an erasable and programmable ROM (EPROM) is mounted on a printed circuit board after writing data therein. On the other hand, an EEPROM is subjected to data rewrite in a state where it is mounted on a printed circuit board. For this reason, an endurance (the possible number of times that data is repeatedly rewritten) is an important factor.
A conventional EEPROM is illustrated in FIGS. 1A, 1B, 1C and 2. Referring to FIG. 1A, there is illustrated a structure of a memory transistor of EEPROM. The illustrated EEPROM 1 includes a semiconductor substrate 2, in which a source region 3 and a drain region 4 are formed. A control gate 5 is formed of polysilicon and is electrically insulated from the substrate 2. A floating gate 6 is formed between the control gate 5 and the drain region 4. A thin oxidation film (tunnel oxidation film) 7 having a thickness of about 100 angstroms is formed between the drain region 4 and the floating gate 6.
Referring to FIG. 2, memory transistors 11-14 each have the transistor structure shown in FIG. 1A. The memory transistors 11 and 13 are connected to a bit line BL1, and the memory transistors 12 and 14 are connected to a bit line BLn. Select transistors 15-20 select the memory transistors 11-14, respectively. Drive transistors 21-23 apply a predetermined voltage to the gates (control gates) of the corresponding memory transistors to thereby drive them. The drive transistor 21 drives the control gates of the memory transistors 11 and 12, and the drive transistor 22 drives the control gates of the memory transistors 13 and 14. It is noted that the drive transistors 21-23 are formed of the depletion type in order to suppress a voltage drop occurring at the time of data write. As indicated by a block of a broken line having a reference numeral 1.sub.1, 1.sub.n, 2.sub.1 or 2.sub.n (n is an integer), one memory transistor and one select transistor configure one bit. A one-dotted chain line which includes the one-bit blocks 1.sub.1 -1.sub.n correspond to one byte. WL1 - WLn indicate word lines, BL1 - BLn indicate bit lines, and PL indicates a program line for controlling the control gates of the memory transistors 11-14. V.sub.CG is a voltage of the program line PL. V.sub.SS is a low-potential side power source or indicates the voltage thereof (ground (GND) for example).
One byte indicated by the one-dotted chain line is selected as follows. The word line WL1 is turned ON, and the bit lines BL1-BLn are set to a predetermined potential. In response to this change of the word line WL1, the select transistors 15 and 16 and the drive transistor 21 are turned ON, and a voltage is applied to the drains of the select transistors 15 and 16. When the predetermined voltage V.sub.CG is applied to the program line PL, this voltage is applied to the control gates of the memory transistors 11 and 12. At this time, the drive transistor 21 is ON because the word line WL1 is ON. Data read is executed by making a decision on whether currents pass through the memory transistors 11 and 12.
However, the aforementioned EEPROM has disadvantages arising from an arrangement that the voltage V.sub.CG is applied to not only the selected memory transistors but also non-selected memory transistors when data is read out. The disadvantages caused by the above-mentioned arrangement will be described in detail below.
As described previously, the drive transistors 21-23 for driving the control gates of the memory transistors 11-14 are of the depletion type (normally ON). Thus, when it is requested to read out data from the memory transistors 11 and 12 and the voltage V.sub.CG (2-4 volts for example) is applied to the program line PL, not only the drive transistor 21 relating to the selected memory transistors 11 and 12 but also the drive transistors 22 and 23 relating to the non-selected memory transistors are turned ON. As a result, the voltage V.sub.CG is applied to the control gates of the non-selected memory transistors 13 and 14. If data stored in the memory transistor 13 causes it to maintain ON, a voltage of 0 volt is applied to the source and drains thereof when V.sub.SS =0 volt. At this time, voltages shown in FIG. 1B are applied to the control gate 5 and the drain region 4 of the memory transistor 13 although it is not selected. Even in a standby state, a voltage is applied to the control gates of all the memory transistors as shown in FIG. 1B.
The state of the memory transistor 11 observed at this time is schematically illustrated in FIG. 1C. In FIG. 1C, C1 is a coupling capacitance between the control gate 5 and the floating gate 6, C2 is a coupling capacitance between the floating gate 6 and the drain region 4, and Q is an accumulated charge. A voltage V applied to the thin oxidation film is calculated as follows. First, following formula (1) is obtained due to the fact that the accumulated charges must be conserved: EQU C1.times.(V.sub.CG -V)+Q=C2.times.(V-V.sub.D) (1)
where V.sub.CG is the voltage of the control gate, and V.sub.D is the drain voltage. From formula (1), the voltage (V-V.sub.D) applied to the thin oxidation film 7 is represented as follows: EQU V=(C1V.sub.CG +C2V.sub.D +Q)/(C1+C2) EQU V-V.sub.D =[Q+C1(V.sub.CG -V.sub.D)]/(C1+C2) (2)
It can be seen from formula (2) that the larger the potential difference .vertline.V.sub.CG -V.sub.D .vertline., the larger the voltage V applied to the thin oxidation film 7. When the storage data of a non-selected memory transistor causes it to maintain ON, the charge Q is a positive charge. When the voltage V.sub.CG equal to 3 volts and the voltage V.sub.D equal to 0 volt are being applied to the non-selected memory transistor, a considerably high voltage is applied to the thin oxidation film 7 thereof. In this state, the positive charge Q is liable to pour into the drain region 4 through the thin oxidation film 7. This effect functions to decrease the data holding time of the non-selected memory transistor.
FIG. 3 is a graph illustrating the relationship between a variation .DELTA.Vth of the threshold voltage Vth of a memory transistor and the bias applying time. It can be seen from the graph of FIG. 3 that the larger the voltage difference .vertline.V.sub.CG - V.sub.D .vertline., the larger a variation .DELTA.Vth where V.sub.th is the difference between a threshold voltage in the initial state and a threshold voltage in the data erase or write state as shown in FIG. 5.
FIG. 4 is a graph illustrating the relationship between the data holding time (log. scale) and the voltage difference .vertline.V.sub.CG -V.sub.3 .vertline.. It can be seen from the graph of FIG. 4 that the data holding time decreases with an increase of the voltage difference .vertline.V.sub.CG -V.sub.D .vertline.. It can be seen from the above discussion that a reduction of the variation .DELTA.Vth with respect to the data readout time contributes to an improvement of the data holding time.
FIG. 6 is a graph illustrating the relationship between the data holding time and the number of times that data is repeatedly rewritten. It can be seen from the graph of FIG. 6 that the data holding time decreases with an increase of the number of times that data is repeatedly rewritten.
As described above, since the voltage difference .vertline.V.sub.CG -V.sub.D .vertline. is large in the non-selected memory transistor at the time of data read and in the standby state, it is difficult to improve the data holding time and provide an increased number of times that data can be erased or written.